A Fault Injection Technique for VHDL Behavioral-Level Models

Fault injection is an important technique for the evaluation of design metrics such as reliability, safety, and fault coverage. Fault injection involves inserting faults into a system and monitoring the system to determine its behavior in response to the fault. Recently, designers are realizing the advantages of using simulation to perform fault injection on a model of the design, as opposed to performing the fault injection on the actual system. As designs become more complex, the need arises to perform fault injection at earlier stages in the design process, specifically at the behavioral level of abstraction where a functional description exists for the various components of the design, but the implementation details have not been developed. A technique has been developed that allows for the injection of faults into a Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) behavioral-level model. The corruption of a VHDL signal (the fault injection) is accomplished using a bus resolution function (BRF) and an additional process statement that performs the fault injection. This process corrupts the VHDL signal based on information read from a text file. The file contains the time to start the fault injection, the time to end the fault injection, which signal to corrupt, and how to corrupt the signal (for example, which bits to stick at a 1, which bits to stick at a 0, and which bits are not affected). This paper outlines the implementation of the fault injection technique using VHDL and demonstrates the use of the technique to evaluate a design. In this case, the design is an embedded control system used to provide fail-safe operation in the railway industry. The paper describes how the technique was used to evaluate the control system and provides the results obtained from the fault injection experiments performed on the control system.